Automatic test equipment plays a key role in the manufacture of semiconductor devices. More commonly called “testers”, the equipment allows manufacturers to test each device for engineering characterization and/or production validation. Ensuring that every device entering commerce “works” is critical for the continued success of a semiconductor device manufacturer.
Unfortunately for the device manufacturer, test comes at a price. Typically, the more complex the device-under-test (DUT), the higher the cost to test it. Cost of test is one of the more important factors in deciding the type of tester to employ in the factory.
Much of the cost of a semiconductor tester is wrapped into the channel architecture. A channel may be thought of as the electronic resources in the tester that interface with one pin of the device-under-test (DUT). If the DUT pins require high performance and high accuracy test signals in order to adequately test the part, each channel may require a host of costly enabling features to achieve the performance. On the other hand, a channel architecture may be greatly simplified, and less costly, if the performance parameters are low.
Typically, as shown generally in FIG. 1, the conventional channel architecture for a semiconductor tester includes AC test circuitry in the form of an AC driver 10 responsive to a pattern generator 12, and DC test circuitry including a DC parametric measurement unit 14. Generally, the AC driver generates and drives AC and test waveforms along a transmission line 16 to a DUT 18, while the DC test circuitry forces a DC voltage or current to the DUT and performs various DC measurements. Usually, tests are performed on the tester at separate times.
Referring now to FIG. 2, which illustrates the conventional channel architecture in further detail, the AC driver circuitry 10 couples to the DUT 18 via the transmission line 16 with a complementing comparator circuit 20. The comparator circuit captures signals from the DUT 18 that are generated in response to the AC driver waveforms. The captured signals are then compared to expected signals to determine whether the DUT functioned as expected.
Further referring to FIG. 2, the DC test circuitry 14 comprises a separate circuit known as a per-pin-parametric-unit, or PPMU. The unit employs an amplifier 22 responsive to a multiplexer 24 that selectively provides one of two DC levels Vin1 (a forcing voltage level) or Vin2 (a “safe” voltage such as ground). A register 26 provides the control signal input to the multiplexer. Disposed at the output of the amplifier is a current measuring circuit comprising a second amplifier 28 with a current sense resistor R. In general, the PPMU provides a force/measurement functionality for DC voltage and current testing of the DUT 18. Consequently, because of its inherent DC characteristics, the PPMU is typically a low-cost circuit.
While this general architecture works well for its intended applications, the cost and size of the hardware to realize the separate AC and DC driver circuits 10 and 14 is often prohibitive for very low-cost and low-performance testers, such as design-for-test (DFT) testers. Thus, the need exists for a low-cost channel architecture for low-cost and low-performance testers. The pin driver circuit of the present invention satisfies these needs.